摘 要如今的电子技术迅猛发展，现在的抢答器功能越来越强大，准确性和可靠性 也得到了提高。之前的抢答器很大一部分都是基于传统数字电路来组成的。其制 作过程相对比较复杂，而且可靠性和准确性也不是很高，成品体积大，安装和维 修也比较困难。由于这几年电子技术迅速发展，渐渐出现了用现场可编辑逻辑门 阵列来制作智能抢答器，使得电子系统的设计者利用 EDA 软件就可以独立设计出 自己的专用集成电路器件。其制作的过程也相对简单，并且安装和维修也简单。69585
本文主要介绍了一种基于 FPGA 并且在 QuartusⅡ工具软件环境下使用 Verilog 硬件编写的数码管显示 4 路智能抢答器的电路设计。
本次设计的智能抢答器可以同时供应四组选手进行抢答比赛，分别使用四个 按钮 a，b，c，d 来表示，需要设置系统复位开关和抢答控制开关，这些都是由 主持人控制。主持人在允许抢答以后，计时器从 30 秒开始倒计时，直至有人抢 答成功以后，数码管上显示抢答成功的选手编号，同时对应选手的 LED 灯也将被 点亮。在判别选手是否回答正确之后，由主持人控制加减按钮进行给分。一轮比 赛结束之后，主持人按下复位按钮，则除了计分模块外，其他模块都复位到初始 时刻，为下一轮的比赛做好准备。
系统芯片主要采用 EP3C25F324C8，由抢答判别模块，计时模块，分频器模 块，计分模块，锁存器模块，数码管驱动模块组成。经过编译及其仿真所设计的 程序，该设计的抢答器基本能够实现此设计的要求，从而完成了抢答器应具备的 功能。
该论文有图 19 幅，表 4 个，参考文献 20 篇。
毕业论文关键词：抢答器 数码显示 硬件描述语言 可编程逻辑门阵列
Design Of Competition System Based On FPGA
Abstract With the development of electronic technology, the responder function is now more powerful, accuracy and reliability is improved. Before the responder a large part is based on the traditional digital form. The production process is relatively complex, and the reliability and accuracy is not very high, the product covers an area of large, installation and peacekeeping is also more difficult. Due to the recent years with the rapid development of electronic technology, gradually comes with a field programmable gate array logic to make intelligent vies to answer first, the designers of electronic systems using EDA software to design their own application specific integrated circuit device. The process is relatively simple, and easy to install and maintain.
This paper mainly introduces a kind of using EDA technology, based on FPGA and under the Quartus II software environment using Verilog prepared by the digital tube display circuit design of 4 intelligent vies to answer first.
The design of intelligent responder can also supplies four groups of players vies to answer first game, respectively, using the four buttons a, b, c, d.At the same time need to set up a system reset switch and Responder control switch, which is controlled by the moderator. Host after allowing the responder, timer is started from 30 seconds countdown until people answer. This is digital tube display answer in the success of the contestant numbers, at the same time, the corresponding player LED lights will be lit up. After judging whether the correct answer, the host controls the addition and subtraction button to give points. After the end of the game, the host press the reset button, in addition to the scoring module, the other modules are reset to the initial moment, to prepare for the next round of the game.
Chip system mainly using EP3C25F324C8. By responder identification module, timing module, frequency pider module, scoring module, latch module, digital tube driver module. After compilation and simulation design program, design of the 基于FPGA竞赛系统设计+程序:http://www.751com.cn/zidonghua/lunwen_78557.html